Các anh chị giúp em bài tập này với: Em đọc mãi mà không làm được
Giúp em với!!!
Mã:
Pipelining and Bypass. In this question we will explore how bypassing affects program
execution performance. To begin consider the standard MIPS 5 stage pipeline. For your
reference, refer to the figure below. For this question, we will use the following code to
evaluate the pipeline’s performance:
1 add $t2, $s1, $sp
2 lw $t1, $t1, 0
3 addi $t2, $t1, 7
4 add $t1, $s2, $sp
5 lw $t1, $t1, 0
6 addi $t1, $t1, 9
7 sub $t1, $t1, $t2
a) What is the load-use latency for the standard MIPS 5-stage pipeline?
b) Once again, using the standard MIPS pipeline, identify whether the value for each register
operand is coming from the bypass or from the register file. For clarity, please write REG or
BYPASS in each box.
c) How many cycles will the program take to execute on the standard MIPS pipeline?
d) Assume, due to circuit constraints, that the bypass wire from the memory stage back to the
execute stage is omitted from the pipeline. What is the load-use latency for this modified
pipeline?
f) How long does the program take to execute on the modified pipeline?
